ID:13502 Verilog HDL Event Control warning at <location>: Event Control contains a complex event expression

CAUSE: In a Verilog Design File (.v) at the specified location, there is an Event Control with an event expression that is not a simple identifier or a concatenation of simple identifiers. Complex event expressions can cause subtle mismatches between the simulated behavior of the design and the synthesized netlist. For example, consider the following Verilog HDL code, which contains a single Always Construct guarded by an Event Control with a complex event expression:

reg data, enable, bad_latch;

               
always@( data && enable ) begin
	bad_latch = data;
end

            

A Verilog simulator executes the Always Construct whenever the value of the expression (data && enable) changes value, effectively creating a pseudo-latch. Quartus Prime Integrated Synthesis, however, ignores the pseudo-latch behavior implied by the Event Control and implements purely combinational logic for the Always Construct.

ACTION: To avoid any potential mismatch between the simulated behavior of the design and the synthesized netlist, remove the complex event expression from the Event Control. The Event Control should contain only simple identifiers or concatenations of simple identifiers. For the previous example, you should use the following code to implement a latch:

reg data, enable, good_latch;

               
always@( data or enable ) begin
	if(enable) good_latch = data;
end