ID:13539 Verilog HDL Case Statement warning at <location>: can't check case statement for completeness because the case expression has too many possible states

CAUSE: At the specified location in a Verilog Design File (.v), you used a case statement whose case expression represents more than 2^32 states. However, Quartus Prime Integrated Synthesis checks only the completeness of case statement with fewer than 2^32 states. As a result, Integrated Synthesis assumed your case statement was incomplete and used the default case item, if present. If you did not specify a default case item, then Integrated Synthesis may infer latches for the assignments in the case statement.

ACTION: No action is required. To remove the warning, reduce the size of the case expression. Otherwise, to avoid unintentional latches, add a suitable default case item or the full_case synthesis attribute to your case statement.