ID:17459 Verilog HDL warning at <location>: case <string>equality operator always evaluates to <string> due to comparison with x or z

CAUSE: Quartus Prime Integrated Synthesis generated the specified warning message for the specified location in a Design File.

ACTION: No action is required. To remove the warning, address the issue identified by the message text. A future version of the Quartus Prime software will provide more extensive Help for this warning message.