ID:13282 Verilog HDL or VHDL warning at <location>: combinational loop detected on net "<name>"

CAUSE: The specified net in the design creates a combinational loop, which may cause unpredictable design behavior.

ACTION: Examine the logic that drives the specified net to identify paths that create a combinational loop. Often, the combinational loop results from incomplete assignments to the signal or variable this net represents, so you may want to check your HDL source. If you intended to infer a latch for the specified net, follow the guidelines for inferring latches outlined in the Quartus Prime Handbook.