ID:13543 Verilog HDL Synthesis Attribute warning at <location>: ignoring full_case attribute on case statement with explicit default case item

CAUSE: In a case statement at the specified location in a Verilog Design File (.v), you specified the full_case synthesis attribute on a case statement with a default case item. Quartus Prime Integrated Synthesis ignored the full_case synthesis attribute as redundant.

ACTION: No action is required. To eliminate the warning, remove the full_case synthesis attribute or remove the default case item.