ID:13438 Verilog HDL Case Statement warning at <location>: case item expression never matches the case expression

CAUSE: In a case statement at the specified location in a Verilog Design File (.v), you used a case item expression that does not match any of the possible values of the case expression. As a result, Quartus Prime integrated Synthesis ignored the case item expression. The case item expression may have more significant bits than the case expression, or it both expressions may have constant bits that do not match. For example, the following case statement has a 3-bit case expression but also contains the 4-bit case item expression 4'b1100.

case({a,b,c})
4'b1100: o = a;
..
..
endcase

            

During elaboration, the case expression will be padded with 1'b0 to match the size of the case item expression. Thus, the most-significant bit of the case expression (0) does not match the most-significant bit of the case item expression (1).