ID:13540 Verilog HDL warning at <location>: case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness

CAUSE: In a case statement at the specified location in a Verilog Design File (.v), you used case item expressions that overlap or potentially overlap. The expressions may potentially overlap if they contain references to variables or nets. Otherwise, they overlap because of don't care bits. In either case, Quartus Prime cannot analyze your case statement for completeness and will assume it to be incomplete, unless otherwise instructed by a full_case pragma or a SystemVerilog unique/priority keyword.

ACTION: If you require a complete case statement, add an explicit default case item. You can force completeness without a default case item by adding a full_case pragma or a SystemVerilog unique/priority keyword.