ID:188026 The Fitter failed to successfully route the design. View the Global Router Wire Utilization Map in the reports GUI and/or Routing Utilization in the Chip Planner to diagnose routing congestion. Based on the congestion information, modify your RTL or compiler settings to improve routability. Consult Intel Quartus Prime help about this message ID for more detailed advice.
CAUSE: The Fitter was unable to route the design because it requires too many device routing resources.
ACTION: There are multiple ways to diagnose or resolve a routing problem. Use one of the following methods to diagnose the routing problem:
- View the Global Routing Wire Utilization Map in GUI for overall routing congestion.
- View the Report Routing Utilization in Chip Planner for detailed routing congestion.
- Investigate signals identified by the router.
- Turn off timing optimization or alternatively just hold optimizations to see if timing constraints are the issue.
- Investigate non-global large fanout nets.
- Reduce routing demand by modifying the design. Reduce the interconnect complexity by localizing routing as much as possible. For example, transform a cross-bar interconnect into a ring-style interconnect to reduce interconnect complexity and improve routability (at the cost of increasing latency).
- If a global signal is unroutable, then delete global promotion of that signal.
- Add or remove Logic Lock regions.
- Reduce very aggressive timing constraints.
- Cut timing paths on cross-clock transfers.
- Change the Fitter Initial Placement Seed in the Advanced Fitter Settings dialog.
- Enable the Fitter Aggressive Routability Optimizations logic option in the Advanced Fitter Settings dialog.
- Reduce logic utilization.
- Select a larger device.