ID:10929 The Fitter is disabling hold optimization on the following clock transfers, because the estimated amount of delay added for hold on these transfers is too large. Usually this is due to bad timing constraints (e.g. missing multicycle, false path on the transfers). For more information, refer to the "Ignored Clock Transfers Due to Huge Delay Added for Hold" section in the Fitter report. If you want to force hold optimization on these transfers, set the ENABLE_HOLD_BACK_OFF setting to OFF.

CAUSE: These clock transfers have too much delay added for hold, so the fitter chooses to ignore the hold requirement on these clock transfers. This may be due to bad timing constraints.

ACTION: Verify that timing constraints, particularly multicycles, are set properly or if the timing constraints are correct, set the ENABLE_HOLD_BACK_OFF setting to OFF to optimize these paths for hold as well.