ID:202000 An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool.

CAUSE: You directed the Quartus Prime software to generate an output netlist file for the top-level design entity. However, the design has PLL atoms. Selecting a timescale other than 1ps will cause the PLL to function incorrectly when the user simulates the design in a third party tool.

ACTION: Change the timescale in the EDA Tool Settings for Simulation Tools to 1 ps.