ID:335093 The Timing Analyzer is analyzing <number of latches> combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Synthesis report.

CAUSE: The Timing Analyzer found latches implemented using non-optimal resources (look-up tables (LUTs) with combinational feedback). The Timing Analyzer replaces the combinational loop with an equivalent latch. The Timing Analyzer treats this logic as a synchronous endpoint, and will not analyze the path through the node.

ACTION: You must implement these latches with registers using asynchronous load and data signals, or remove them from your design. For more information, run the check_timing tcl command in the Timing Analyzer.