ID:332081 Design contains combinational loop of <number> nodes. Estimating the delays through the loop.

CAUSE: The Timing Analyzer found a combinational loop of the specified number of nodes that exceeds the default MAX_SCC_SIZE specification for the current project. Combinational loops are loops in combinational logic, with no registers between any of the nodes. The Timing Analyzer analyzes combinational loops very conservatively in order to ensure that only legitimate timing violations are detected in the design. Accurate timing analysis becomes more difficult as loop size increases above ten. Large combinational loops also decrease the effectiveness of timing-driven compilation. Large combinational loops are usually the result of a design error. When this condition occurs, the Timing Analyzer only estimates the delay through the loop.

ACTION: If this loop is intentional, you can change the number of nodes in a loop that the Timing Analyzer will analyze by specifying a value for the MAX_SCC_SIZE timing assignment. However, specifying a very high value for this assignment may result in extremely long analysis times and inaccurate analysis. If the loop is unintentional, examine the design to see if the loop is involved in logic paths that are not meeting timing, and remove the loop from the design.