ID:332125 Found combinational loop of <number> nodes

CAUSE: The Timing Analyzer found a combinational loop of the specified number of nodes in the netlist. Combinational loops may be caused by design errors. For example, by the incorrect use of an If Statement (VHDL), If Then Statement (AHDL), or If-Else Statement (Verilog HDL) in a design file. Combinational loops are loops in combinational logic, with no registers between any of the nodes. The Timing Analyzer analyzes combinational loops very conservatively in order to ensure that only legitimate timing violations are detected in the design. Accurate timing analysis becomes more difficult as loop size increases above 10. Large combinational loops also decrease the effectiveness of timing-driven compilation. Large combinational loops are usually the result of a design error. When this condition occurs, the Timing Analyzer only estimates the delay through the loop. Additional messages list the names of the nodes in the loop.

ACTION: If the combinational loop is intentional, no action is required. If you want to eliminate the combinational loop, check your source files and make sure that all If Statements have a corresponding Else Statement, examine the design to see if the loop is involved in logic paths that are not meeting timing, and remove the loop from the design.