ID:332082 All paths through the combinational loop are disabled.

CAUSE: The Timing Analyzer found a combinational loop and is ignoring all paths through the loop. Combinational loops are loops in combinational logic, with no registers between any of the nodes.

ACTION: If the loop is unintentional, examine your design to verify if the loop is involved in logic paths that are not meeting timing, and then remove the loop from your design.