ID:332189 derive_pll_clocks was called multiple times with different options. Repeated calls to derive_pll_clocks do not modify existing clocks.

CAUSE: There were multiple calls to derive_pll_clocks with different options. Only an initial call to derive_pll_clocks creates clocks. All subsequent calls are ignored. If any derived clocks are removed between calls to derive_pll_clocks, the next call to derive_pll_clocks will constrain those clocks with the new options.

ACTION: For best results, use only one call to derive_pll_clocks in your Synopsys Design Constraints File (.sdc). If you changed the options to derive_pll_clocks in your .sdc using the Timing Analyzer GUI, you must call reset_design before re-reading the .sdc.