ID:13004 Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
CAUSE: One or more registers in the design have one of the following conditions:
- The register has both a preset and a clear signal.
- The register has a preset signal but does not have a clear signal, and Analysis & Synthesis turned off the NOT Gate Push-Back logic option.
- The register has an asynchronous load and corresponding data signal.
ACTION: No action is required. If you want to prevent glitches, put KEEP attributes on the asynchronous signals that feeds the register, and on the register itself. This action is necessary only if the asynchronous signals come from combinational logic or if the register feeds combinational logic. Make sure that you perform timing simulation to verify that no unexpected glitches occur.