ID:276020 Inferred RAM node "<name>" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.

CAUSE: You described a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that behave as RAM. Analysis & Synthesis then replaces the registers with a RAM node that will later infer an instance of the altsyncram megafunction to implement the functionality of the registers using the memory blocks in the target device. However, the native read-during-write behavior of the memory blocks does not match the actual read-during-write behavior of your design. During the read and write process from the same address, your design specifies that the read returns the new data, but the memory blocks do not support this behavior. Analysis & Synthesis added an extra bypass logic to guarantee that a read-during-write returns the new data, but the extra logic added by Analysis & Synthesis can decrease performance.

ACTION: If you do not want Analysis & Synthesis to replace your registers with an altsyncram megafunction, turn off the Auto RAM Replacement logic option. If you do not want Analysis & Synthesis to add extra bypass logic, apply the ramstyle synthesis attribute with the value "no_rw_check" to the object representing the RAM in your design file. Alternatively, you can also turn off the Add Pass-Through Logic to Inferred RAMs logic option.