ID:276019 Created node "<name>" as a RAM by generating an altdpram megafunction to implement register logic with MLABs. Pass-through logic has been added.

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified a set of registers that act as a RAM. When Analysis & Synthesis created the specified node as a RAM using the registers, it converted the registers into an altdpram megafunction to implement the register logic with MLABs on the target device you specified for the current design. When simultaneous reading and writing to the same RAM address occurs, the original design specifies that the new value of the RAM address will be read. Analysis & Synthesis added extra logic to guarantee that the new value of the RAM address will be read when simultaneous reading and writing to the same RAM address occurs. The extra logic added by Analysis & Synthesis may decrease performance.

ACTION: If you do not want Analysis & Synthesis to add the extra logic, prevent Analysis & Synthesis from converting the registers into an altdpram megafunction by turning off the Auto RAM Replacement logic option.