ID:276022 Created node "<name>" as a RAM by generating altdpram megafunction to implement register logic with MLABs. Functionality differs from the original design.

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified a set of registers that act as a RAM. When Analysis & Synthesis created the specified node as a RAM using the registers, it converted the registers into an altdpram megafunction to implement the register logic with MLABs on the target device you specified for the current design. The original design specified that writing to the RAM occurs on the rising edge of the write clock. However, writing to the MLABs occurs on the falling edge of the write clock. When simultaneous reading and writing to the same RAM address occurs, the functionality of the MLAB memory block is not identical to the functionality of the RAM in the original design.

ACTION: If you intended Analysis & Synthesis to convert the registers into an altdpram megafunction to implement the register logic with MLABs, and you do not mind if the functionality of the MLAB memory block is not identical to the functionality of the RAM in the original design when simultaneous reading and writing to the same RAM address occurs, no action is required. If you want Analysis & Synthesis to use an altdpram megafunction, but you want to avoid receiving this message in the future, replace the registers and address logic in the Verilog Design File or VHDL Design File with an explicit instantiation of an altdpram megafunction. If you want the functionality of the RAM in the original design to be the same as the functionality that is implemented in the target device, prevent Analysis & Synthesis from converting the registers into an altdpram megafunction by turning off the Auto RAM Replacement logic option.