ID:276025 Inferred RAM node "<name>" from synchronous design logic, but the read-during-write behavior of RAM does not match the read-during-write behavior of the original design

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. When Analysis & Synthesis created the specified node as RAM using the registers, it converted the registers into an altsyncram megafunction to implement the register logic with an M512 memory block, M-LAB memory block, M4K memory block, M9K memory block, M-RAM memory block, or M144K memory block. During simultaneous reading and writing to the same RAM address, the original design specifies that the new value of the RAM address is read. However, an M512 or M4K memory block reads the old value of the RAM address, while an M-RAM reads an undefined value during the same simultaneous reading and writing to the same RAM address.

ACTION: If you intend Analysis & Synthesis to convert the registers into an altsyncram megafunction to implement the register logic with an M512 memory block, M-LAB memory block, M4K memory block, M9K memory block, M-RAM memory block, or M144K memory block, and it is not necessary for the functionality of the M512 or M4K memory block or M-RAM to be identical to the functionality of the RAM in the original design during simultaneous reading and writing to the same RAM address, no action is required. If it is necessary for Analysis & Synthesis to use an altsyncram megafunction, but you want to avoid receiving this message in the future, replace the registers and address logic in the Verilog Design File or VHDL Design File with an explicit instantiation of an altsyncram megafunction. If the functionality of the RAM in the original design need to be the same as the functionality that is implemented in the target device, prevent Analysis & Synthesis from converting the registers into an altsyncram megafunction by turning off the Auto RAM Replacement logic option.