ID:276023 Created node "<name>" as a dual-clock RAM by generating altdpram megafunction to implement register logic with MLABs. However, functionality differs from the original design.

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. When Analysis & Synthesis created the specified node as RAM using the registers, it converted the registers into an altdpram megafunction to implement the register logic with MLABs on the target device you specified for the current design. However, the RAM write clock and read clock differ, and when simultaneous reading and writing to the same RAM address occurs, the behavior of the MLABs is undefined. Thus the functionality of the MLAB memory block is not identical to the functionality of the RAM in the original design when simultaneous reading and writing to the same RAM address occurs.

ACTION: If you intended Analysis & Synthesis to convert the registers into an altdpram megafunction to implement the register logic with MLABs, and you do not mind that the functionality of the MLAB memory block is not identical to the functionality of the RAM in the original design when simultaneous reading and writing to the same RAM address occurs, no action is required. Avoid receiving this message in the future by adding a no_rw_check ramstyle synthesis attribute to the RAM in the Verilog Design File or VHDL Design File. Alternatively, replace the registers and address logic in the Verilog Design File or VHDL Design File with an explicit instantiation of an altdpram megafunction. If you want the functionality of the RAM in the original design to be the same as the functionality that is implemented in the target device, prevent Analysis & Synthesis from converting the registers into an altdpram megafunction by turning off the Auto RAM Replacement logic option.