ID:276035 Created node "<name>" as a RAM by generating altdpram megafunction to implement register logic with MLABs. Expect to get an error or a mismatch for this block in the formal verification tool.

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified a set of registers that act as RAM. When Analysis & Synthesis created the specified node as RAM using the registers, it converted the registers into an altdpram megafunction to implement the register logic with an MLAB memory block on the target device you specified for the current design. This memory block is a new instance that is handled as a black box by the formal verification tool. However, no such instance exists in the original design. This results in the formal verification tool reporting mismatches or errors.

ACTION: If you intended this conversion and implementation and do not mind if the formal verification tool reports a mismatch or an error, no action is required. If you want Analysis & Synthesis to use an altdpram megafunction, but you want the formal verification tool to verify the rest of the design, replace the registers and address logic in the Verilog Design File or VHDL Design File with an explicit instantiation of an altdpram megafunction. Note that if the register and address logic in an entity are treated as a black box and the entity is parameterized, create a wrapper entity that does not contain parameters. If you want the RAM in the original design to function the same as the RAM implemented in the target device and want to verify the design including the RAM, prevent Analysis & Synthesis from converting the registers into an altdpram megafunction by turning off the Auto RAM Replacement logic option.