ID:14997 The FPGA to HPS SDRAM PLL reference clock path is not timing analyzed and could be subject to jitter.

CAUSE: Intel does not recommend using the FPGA to HPS SDRAM PLL, since it could be subject to jitter.

ACTION: Disconnect the FPGA to HPS SDRAM PLL (f2h_sdram_ref_clk) and use the one of the HPS dedicated Clock pins as a reference clock instead (HPS-CLK1 or HPS-CLK2)