ID:18061 Ignored Power-Up Level option on the following registers

CAUSE: You set the Power-Up Level option for one or more registers. However, the power-up level cannot be honored. For example, if registers do not have asynchronous load capability on the chosen device, then a register that uses asynchronous clear cannot power up to High. Similarly, if registers do not have asynchronous load capability on the chosen device, then a register that uses asynchronous preset cannot power up to Low. Note that Quartus Prime Integrated Synthesis reads default values for registered signals defined in VHDL code and converts the default values into Power-Up Level settings. The software also synthesizes variables that are assigned values in Verilog HDL initial blocks into power-up conditions. Click the + icon to expand this message in the Messages window or the Messages section of the Report window to determine which registers had the Power-Up Level option ignored.

ACTION: No action is required. To avoid receiving this message in the future, either turn off or delete the Power-Up Level option for the registers or modify the design so that the register can power-up to the specified level.