ID:176600 Transceiver PLL "<name>" input clock inclk[<number>] may have reduced jitter performance while used for transceiver channels that configured at a data rate that is higher or equal to 2.97 Gbps because it is fed by a clock pin "<name>"

CAUSE: Transceiver channels are configured at a data rate that is higher or equals to 2.97 Gbps which requires that you follow updated pin connection guidelines. For technical details on the updated pin connection guidelines and to download a patch to continue compilation, refer to Intel FPGA Knowledge Database solution number rd10182010_86.

ACTION: Contact Intel Technical Support for a workaround for successful compilation.