ID:176272 Can't pack node "<name>" and I/O cell <name>. The node and I/O cell are connected across a Design Partition boundary.

CAUSE: You turned on both the Auto Packed Registers logic option, and the Fast Input Register , Fast Output Register , and/or Fast Output Enable Register logic options for the specified nodes. The specified node can also be a PLL compensated pin in source synchronous mode. However, the Quartus Prime software cannot pack the nodes. Doing so would modify the interface of one or more Design Partitions.

ACTION: If the node is packed, you must restructure your HDL and/or Design Partition assignments. See the "Quartus Prime Incremental Compilation" chapter in Volume 1 of the Quartus Prime Handbook for details on restrictions imposed on Register Packing by Design Partitions. If the node is not packed, turn off the Fast Input Register, Fast Output Register, or Fast Output Enable Register option on the node or I/O cell or remove the PLL source synchronous mode assignment on the I/O cell.