ID:176232 Can't pack node "<name>" and I/O node "<name>" -- resulting I/O placement would violate pin assignment rules

CAUSE: You turned on the Auto Packed Registers logic option, and turned on the Fast Input Register , Fast Output Register , and/or Fast Output Enable Register logic options for the specified nodes. The specified node can also be a PLL compensated pin in source synchronous mode. However the Fitter cannot pack the nodes as a fast register pair because applying the LCELL node's location assignment to the I/O node would force a violation of the pin assignment rules. The location assignments may be direct, such as a user location assignment or pin assignment, or they may be indirect. For example, a register could acquire an indirect location constraint if one of its control signals is driven by a signal promoted to a Regional Clock or Fast Regional Clock network.

ACTION: To determine the pin assignment conflict, apply the LCELL location assignment to the I/O node and use the I/O Assignment Analysis tool. If the I/O node settings are correct, then modify or remove the location assignment on the LCELL node, or turn off the Fast Input Register, Fast Output Register, or Fast Output Enable Register assignment on either the I/O node or the lcell node. If the LCELL register is being driven by a signal promoted to a Regional Clock network or Fast Regional Clock network (for example, because the clock is driven by a PLL), then it may help to explicitly promote that clock signal to Global Clock because Global Clock networks drive the entire device.