ID:176269 Can't pack node "<name>" -- pin "<name>" is a DQ input and packing the register into the I/O cell reduces the DQ timing margin

CAUSE: You turned on the Fast Input Register logic option for the specified logic cell or pin. However, the pin is a DQ input, and the register is one of two DQ input capture registers for the DQ input pin. Packing one of the capture registers into the I/O cell reduces the timing margin below acceptable limits.

ACTION: Remove the Fast Input Register logic option assignment on the node.