ID:176123 Input clock frequency for PLL "<name>" is not the same as the core clock frequency of PLL "<name>"

CAUSE: The Fitter is reporting that the input clock frequency for the specified PLL differs from the core clock frequency of the other specified PLL.

ACTION: No action is required. If you want to merge these PLLs, modify the design to make the input clock frequency of the PLL being driven is the same as the core clock frequency of the driving PLL.