ID:176077 Can't merge PLL <name> and PLL <name> -- PLLs contain a total of <number> unique counters of which <number> drive external clock output pins, but only one is allowed

CAUSE: The Fitter tried to merge the specified PLLs that contain the specified number of unique counters driving the specified number of external clock output pins. However, the Fitter cannot merge the PLLs because only a single PLL counter can drive external clock connections.

ACTION: Modify the design so that only a single different value PLL counter drives external clock output pins.