ID:176597 Corner PLL "<name>" input clock inclk[<number>] is not fully compensated because it is fed by a center pin "<name>"
CAUSE: The specified PLL is a corner PLL and its specified input clock is driven by a center input pin. As a result, the input clock delay will not be fully compensated by the PLL.
ACTION:
- No action is required if you do not care about compensation of the specified input clock.
- For compensation of the specified input clock, connect the input clock to a dedicated corner clock input pin.