ID:176575 Cannot implement <name> PLL "<name>", because the input clock of the PLL "<name>" uses I/O standard <name> and has a frequency of <name>. However, the device only supports a frequency up to <name>.

CAUSE: You specified the input clock frequency and the specified I/O standard for the specified input pin, which is an input clock of the specified fast or enhanced PLL. However, the input clock frequency is higher than the maximum input clock frequency the target device supports for the I/O standard.

ACTION: Modify the design so that the input clock frequency of the PLL is less than the maximum input clock frequency, which the target device supports for the I/O standard.