ID:16067 <number> out of <number> DSP block(s) in the design are not fully utilizing recommended internal DSP register banks. Design performance may be limited. To take full advantage of device resources, you should either enable the register banks directly (if using WYSIWYG entry) or provide additional registers in your design that the Quartus register packing optimization algorithm can convert to internal DSP register banks. The "Fixed Point DSP Register Packing Details" Fitter report indicates which DSP blocks are affected.
CAUSE: The DSP Register Packer was unable to fully utilize all the recommended internal register banks (input, pipeline and output) in some DSP blocks in the design.
ACTION: Please refer to Altera Megafunctions/LPM on instantiating parameterized DSP modules that fully utilize internal DSP register banks. Please refer to "Fixed Point DSP Register Packing Details" table in the Fitter Report for more information on DSP blocks in your design. Please refer to Intel FPGA Documentations for more information on Altera DSP architectures for your device family.