ID:18411 One or more registers failed to be packed into a DSP bank due to conflicting use of synchronous and asynchronous clears

CAUSE: DSP blocks support the use of either synchronous or asynchronous clear, but not both at the same time. Could not pack some registers due to mixed use of synchronous and asynchronous clear.

ACTION: Please refer to "Fixed Point DSP Register Packing Details" table in the Fitter Report to determine which DSP blocks were affected. Ensure candidate registers for packing into a DSP all use only one type of clear (either synchronous or asynchronous).