ID:176345 Worst-case clock duty cycle of a GXB receiver channel clkout and a GXB transmitter channel clkout in CPRI Protocol can be 60/40 percent

CAUSE: The design contains a gigabit transceiver block (GXB) using the CPRI Protocol. The worst-case clock duty cycle of a GXB receiver channel clkout and a GXB transmitter channel clkout can be 60/40 percent because of timing constraints for the CPRI Protocol.

ACTION: Make sure that your design uses positive edge clocking only on these clock signals or apply the correct clock duty cycle Timing Analyzer constraints for your timing analysis. If these clock signals will be sent off-chip to clean up for re-timing purposes, you should choose a VCXO-based PLL that can tolerate an input clock with a clock duty cycle of 60/40 percent.