ID:176683 Placing a CK or a CKn pin pair on <name> and <name> at the same row and column as the DQ pins may result in failure to constrain the DDIO Input nodes to improve DDIO timing

CAUSE: You made a pin location assignment on the CK and CKn pins at the same row or column as the DQ pins, but this placing may result in failure to constrain the DDIO Input nodes due to clock limits.

ACTION: You can remove the pin location assignments or change the pin location assignments to avoid this warning in the future.