ID:16657 Could not find solution for <number> of <number> core register(s) constrained <text>. Placement and routing for these <number> connection(s) were not committed -- please relax the constraint.

CAUSE: You specified one or some of the following core-periphery transfer optimization constraints: Max Delay for Core Periphery Transfer, Min Delay for Core Periphery Transfer assignments, Max Wires for Core Periphery Transfer, Min Wires for Core Periphery Transfer assignments, however, the constraint you set is too hard to meet.

ACTION: Relax or remove one of the assignments. You must set these options in the Quartus Prime Settings File (.qsf).