ID:308020 (Medium) <text>. Found <number> ripple clock structure(s) related to this rule.

CAUSE: In the current design, the Design Assistant found the specified number of ripple clock structures, which are structures where the outputs of two or more registers in a cascade each directly drives the input clock port of the following register in the cascade. However, designs should not contain ripple clock structures. Each stage of a ripple clock structure causes phase delay, which accumulates and results in large skews in the structure's output signal. The large skew can cause problems when you use the ripple clock structure as a clock signal for other circuits. Each stage of a ripple clock structure also causes a new clock domain to be defined; the additional clock domains make timing analysis of the design more complex and time-consuming. In addition, in all Intel FPGA devices supported by the Quartus Prime software, using a ripple clock structure is unnecessary because the device allows you to construct a counter using one logic element per counter bit. The submessage(s) of this message list the structure(s) that the Design Assistant found.

ACTION: Make sure that no more than one of the register outputs in a cascade directly drives the input clock port of the following register in the cascade.