ID:308051 (Critical) <text>. Found <number> structure(s) related to this rule.

CAUSE: In the current design, the Design Assistant found the specified number of structures that generate multiple pulses in the following way:

• Each structure contains a two-input AND, NAND, OR, or NOR gate.
• The AND or OR gate output drives one of the gate's own inputs through an inverted delay chain (one or more consecutive nodes that act as a buffer for creating intentional delay). or The NAND or NOR gate output drives one of the gate's own inputs through a delay chain.
• A triggering signal drives the gate's other input.

These structures generate widths for the multiple pulses that are difficult for the Quartus Prime software to determine, set, or verify. For example, the pulse widths are difficult for the Quartus Prime software to determine if Analysis & Synthesis and the Fitter have not already determined the node delays necessary for the pulse widths. Also, when a design is converted for a HardCopy device, the generated pulse widths may be different from the pulse widths generated by the design's original device. Structures that generate multiple pulses cause more problems than pulse generators due to the number of pulses involved. In addition, when the structures generate multiples pulses, they also increase the frequency of the design.