ID:308043 (High) <text>. Found <number> node(s) related to this rule.

CAUSE: In the current design, the Design Assistant found the specified number of nodes where you used a logic cell to implement an inverter that drives the input clock port of a register. However, implementing the inverter with a logic cell can lead to clock insertion delay and skew, which can cause problems with the timing closure of the design. In addition, for all Intel FPGA devices supported by the Quartus Prime software, using a logic cell is unnecessary because register clocks in the devices have programmable inverts for implementing inverters. The submessage(s) of this message list the node(s) that the Design Assistant found.

ACTION: Use a register clock's programmable invert to implement an inverter in the design.