ID:308026 (High) <text>. Found <number> node(s) related to this rule.

CAUSE: In the current design, the Design Assistant found the specified number of nodes where a reset signal is generated in one clock domain and used in one or more other, asynchronous clock domains. However, the synchronization of the reset signal does not follow the following guidelines and therefore causes metastability problems in the design:

• The reset signal should be synchronized with two or more cascading registers in the receiving asynchronous clock domain.
• The cascading registers should be triggered on the same clock edge.
• There should be no logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.

A reset signal that is not correctly synchronized can also cause the output of registers in the receiving asynchronous clock domain to send incorrect signals, which can cause primary output pins in the device to momentarily send incorrect signals. The submessage(s) of this message list the node(s) that the Design Assistant found.