ID:15062 PLL "<name>" in Source Synchronous mode with compensated output clock set to clk[<number>] is not fully compensated because it does not feed an I/O input register

CAUSE: The specified PLL is in Source Synchronous mode and its compensated output clock is not feeding an I/O input register. As a result, the output will not be fully compensated.

ACTION: Connect the output clock to an I/O input register that should be compensated. Alternatively, set the PLL to No Compensation mode instead if you do not want compensation.