ID:15059 Settings for PLL "<name>" may result in significant clock output drift over process, voltage or temperature variations

CAUSE: The specified PLL has settings, such as charge pump current and phase frequency detector (PFD) frequency, that may result in high static phase offset variation, or significant clock output drift over process, voltage or temperature variations.

ACTION: To minimize the variation, use medium or high bandwidth settings instead of low bandwidth, or try specifying a higher input frequency. If specifying advanced parameters, increase the charge pump current and PFD frequency.