ID:15039 Input clock pin "<name>" (feeds inclk port of enhanced PLL "<name>") and output pin "<name>" (the compensated clock output) have different I/O standards, <name> and <name>

CAUSE: The I/O standards you assigned to the specified input and output clock pins do not match. The output clock pin, which will be compensated by the specified enhanced PLL, must have the same I/O standard as the input clock pin.

ACTION: Change I/O standard assignments of specified input and output pins so they match.