ID:15549 PLL clock output <name> was implemented with counter that uses odd counter mode or value -- <name> parameter is not satisfied

CAUSE: You specified even counter mode or value control for the specified PLL clock output (that is, either the CLK_USE_EVEN_COUNTER_MODE parameter is set to ON or the CLK_USE_EVEN_COUNTER_VALUE parameter is set to ON), but the Quartus Prime software was not able to achieve the even counter mode or an even counter value for this PLL clock output. This message is a submessage of the message that precedes it in the Messages window and in the Messages section of the Report window.

ACTION: Specify different multiply and divide ratios, or specify a different input frequency that will allow an even counter mode or an even counter value to be achieved.