ID:20086 The port <port name> for DSP block WYSIWYG primitive "<atom name>" is currently connected to VCC. This signal will be fed to a register which is susceptible to any clear signal from the CLR[0] input port.

CAUSE: The specified DSP block WYSIWYG primitive has the specified port connected to VCC. This signal will be fed to a register which is susceptible to any clear signal from the CLR[0] input port.

ACTION: Connect the port to a signal or tie to GND if it is not used.