ID:15710 Ignored I/O standard assignment to node "<name>"

CAUSE: The Fitter ignored the specified I/O standard assignment. Either the node does not exist or the assignment was made on a bus or an entity and then overridden on every bus member.The Quartus Prime software made these assignments due to one or more of the following reasons:

• The assignment was made on a bus or an entity and also on all of its members.
• The design contains old assignments that are no longer valid. Invalid assignments can occur when the source files change.
• The design was previously compiled with Fitter netlist optimizations and then back-annotated. Back-annotation writes out location assignments for any nodes created by Fitter netlist optimizations. However, there is no guarantee that Fitter netlist optimizations will re-create the same nodes on this compile. The recommended method to preserve the results of a compilation with Fitter netlist optimizations on is to back-annotate locations and to use a Verilog Quartus Mapping File (.vqm) to save the netlist changes made by the Fitter.
• The design uses a VQM file as source that was generated from a previous compilation with register packing on and then back-annotated. Back-annotation writes out location assignments for both parts of a packing operation. Because the VQM file represents the netlist after the packing operations have already been performed, one of the assignments may no longer apply.