ID:21300 <name> port on the PLL is not properly connected on instance "<name>". The <name> port on the PLL should be connected when the <name> port is connected. Although it is unnecessary to connect the <name> signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready.

CAUSE: The locked clock port on the PLL should be connected when the feedback output port is connected. Although it is unnecessary to connect the locked clock, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready.

ACTION: Update the design by connecting the locked port of the PLL.