ID:292022 OpenCore Plus time-limited core <name> may be used for hardware evaluation only.

CAUSE: You instantiated the specified OpenCore Plus time-limited core to your project. This core may be used for hardware evaluation only.

ACTION: You will be able to program an Intel FPGA device only with a download cable through the Quartus Prime Programmer, and the design will run for only a given number of clock cycles. See core documentation for clock cycle limits and disable behavior, or see the OpenCore Plus Hardware Evaluation of MegaCore Functions application note, which is available at the Intel FPGA web site for general information. To compile the non-time-limited version of this core, change your User Libraries settings by removing "lib_time_limited" from your core, and adding "lib". You will also need to reinstantiate the core in the design.