ID:127013 Memory width (<number>) in the design file differs from memory width (<number>) in the Memory Initialization File "<name>" -- setting initial value for remaining bits to "don't care"

CAUSE: The memory width value you specified in a design file (Block Design File (.bdf), Text Design File (.tdf), VHDL Design File (.vhd), Verilog Design File (.v), or EDIF Input File (.edf)) of a design does not match the memory width value you specified in the Memory Initialization File (.mif). This condition occurs when you specify a memory width in the design file that is greater than the memory width defined in the Memory Initialization File or the Hexadecimal (Intel-Format) File (.hex) . The Quartus Prime software is therefore setting the initial value for the remaining bits to "don't care".

ACTION: If you do not want the initial value for the remaining bits set to "don't care", make sure that the design file and the Memory Initialization contain the same memory width values for the memory block.